Generalised Space Vector Pulse Width Modulation Method for Multilevel Inverters Including over Modulation Region and Its Implementation with FPGA

The present day automated world has witnessed inexplicable changes that have led to the growth and development of a contemporary technological era. It has become vital on the part of electric utilities to accommodate the necessary changes with a view to accomplish the challenges of the growing application needs. The power electronic interfaces have become an imminent necessity in order to meet the objective. The consequent extensive use of semi-conductor power switches inadvertently generate the acrimonious signals along with the required output that cause deleterious effects  and contaminated with a wide range of harmonics.

The formulation of control strategies have to be efficient to enable the converters in realizing the dictated performance. Pulse width modulation is a signal processing technology works as a key control scheme for the switching elements in power conversion. PWM is regarded as a high frequency energy processing operation performed on the converter switched output voltage/ input current waveform to optimize a specific performance criterion such as minimization of the Total Harmonic Distortion (THD), reduction of lower order harmonics, spreading the harmonic power, loss minimization etc. Most of the known methods of generating PWM signals are based on a comparison between a reference or modulation signal with a suitable carrier, and grouped as natural sample PWM schemes. The space vector modulation (SVM) technique differs from the above methods in a way that there are no separate modulators used for each of the three-phases. This is an advanced and computation intensive PWM technique for multilevel inverters which can accomplish the desired characteristics.

This book provides the comprehensive analysis and implementation of the generalized space vector pulse width modulation method for multilevel converters focused mainly on the most recent advances made in this field in the past few years, covering new promising topologies, modulations, controls and operational issues. Implemented the same in FPGA for cascaded and diode clamped multilevel inverters feeding induction motor load.